1. Field of the Invention
This invention relates to semiconductor device manufacturing and, more particularly, to an improved system and method for fabricating contact openings in a semiconductor topography.
2. Description of the Related Art
The following descriptions and examples are given as background only.
At various stages in the fabrication of semiconductor devices, it is often necessary to form openings in an inter-level dielectric layer to allow for contact to underlying regions or layers. Generally, an opening through a dielectric layer that exposes a diffusion region, or an opening through a dielectric layer between polysilicon and a first metal layer is called a “contact opening” or a “contact hole.” Conversely, an opening through other dielectric layers such as an opening through an inter-metal dielectric layer is generally referred to as a “via.” For purposes of this disclosure, however, the term “opening” may be used herein to refer to a contact opening and/or a via. As such, an opening may expose a diffusion region within the semiconductor substrate, such as a source or drain region, or may expose other layers or structures, such as an underlying metallization layer, a local interconnect layer, or a gate structure. Subsequently, a contact structure may be formed within the opening by filling the opening with a conductive material to electrically contact the underlying region or layer. In other cases, however, openings may be fabricated to form other structures, such as isolation regions or gate structures, for example.
As the densities of semiconductor devices are continually increased, profile and dimension requirements of semiconductor device features, such as contact structures, must be optimized. In some cases, the amount of space a contact structure consumes may be minimized to increase the density of semiconductor devices. In such a case, it may be desirable for an opening to be formed having sidewalls that are substantially perpendicular to an upper surface of a semiconductor substrate. As such, the sidewall angle of the opening may be at a 90° angle with respect to the upper surface of the semiconductor substrate. Such an opening may exhibit top and bottom lateral dimensions that are substantially uniform. In this manner, a contact structure may be formed within the opening, which may have predictable and desirable dimensions and electrical properties.
In addition, the lateral dimensions of semiconductor features, such as contact structures, may be reduced to increase the density of devices on a semiconductor substrate. Generally, however, the height of semiconductor features may not be reduced in proportion to the lateral dimensions. In this manner, the aspect ratio of semiconductor features may be higher for advanced semiconductor devices that are designed having high device densities. An aspect ratio, as used herein, generally refers to the ratio between the height and width of a semiconductor feature when viewed in cross section. As the aspect ratio of a contact structure increases, it may become increasingly difficult to form openings that maintain acceptable critical dimensions. For example, a high aspect ratio contact structure may be formed having a sidewall angle that deviates substantially from 90° with respect to an upper surface of the semiconductor substrate. In such an example, a bottom lateral dimension of the opening may be smaller than an acceptable critical dimension.
The term “critical dimension,” as used herein, generally refers to the dimensional design value of a semiconductor feature. In some cases, critical dimensions may represent the smallest dimension that may be formed on a semiconductor topography using various fabrication techniques, such as photolithography and etching techniques. In other cases, however, critical dimensions may represent the smallest dimension of a semiconductor feature that maintains optimal operating characteristics of that feature. For example, as stated above, a high aspect ratio opening may be formed having a bottom lateral dimension, which is smaller than an acceptable critical dimension. Such a small bottom lateral dimension may reduce the contact area of the contact structure formed within the opening. A reduction in contact area may lead to numerous problems including, but not limited to, increased electrical resistance between the contact structure and the underlying conductive region or layer. Such an increase in resistance may further lead to a decrease in the speed and reliability of the semiconductor device.
There are several conventional methods for forming contact structures. For example, an opening may be etched through a dielectric layer to expose an underlying region or layer, such as a diffusion region in a semiconductor substrate or a metal interconnect layer. To fully etch the opening without destroying the underlying layer, an etch chemistry may be used which may be selective to the material composition of the underlying layer. As such, the etch chemistry may exhibit a slow etch rate with respect to the material composition of the underlying layer, and a fast etch rate with respect to the material composition of the dielectric layer.
There are, however, several disadvantages to using a selective etch chemistry for forming a contact structure. For example, a selective etch chemistry may deposit a passivating material, such as a polymeric residue or another by-product of the etch process, on the sidewalls of the opening. As such, the use of a selective etch chemistry may cause significant tapering in the sidewall surfaces of the opening. During an etch process, for example, the sidewalls at the top of the opening may be coated with a progressively thicker polymeric residue than the sidewalls at the bottom of the opening. Such an uneven build-up of polymeric residue may shadow the bottom of the opening, thereby resulting in a progressively smaller bottom lateral width of the opening as the etch process continues. After termination of the etch process, the layer of passivating material formed upon the sidewall surfaces of the contact opening may generally be removed using a wet etch process prior to any further processing. However, such passivating materials may be difficult, if not impossible, to remove when an opening with significantly tapered sidewall surfaces is formed having a high aspect ratio. In general, a high aspect ratio may describe a feature, such as an opening, which has a substantially larger height than a width when viewed in cross-section. In some cases, an aspect ratio approximately greater than or equal to 4:1 may be considered a high aspect ratio. In other cases, a high aspect ratio may be approximately greater than or equal to 5:1.
Alternatively, an opening may be formed using an etch chemistry that is not selective to an underlying layer. As such, the etch chemistry may exhibit substantially the same etch rate with respect to the material compositions of the dielectric layer and the underlying layer. Therefore, to etch an opening through the dielectric layer without destroying the underlying layer, as described above, an etch stop layer may be formed between the dielectric layer and the underlying layer. In such a case, the etch chemistry is used to etch through the dielectric layer to the etch stop layer. Complete removal of the etch stop layer, however, is necessary to obtain electrical contact between the contact structure and the underlying layer. Therefore, after etching the opening through the dielectric layer, a second etch process may be performed to remove the remainder of the etch stop layer.
There are, however, several disadvantages to using an etch stop layer for forming a contact structure. For example, using an etch stop layer may reduce the bottom lateral dimension of a contact opening below an acceptable critical dimension. In some cases, the second etch process may insufficiently remove the etch stop layer from sidewall surfaces of the contact opening. In this manner, remaining portions of the etch stop layer may reduce the bottom lateral dimension of the contact opening. As stated above, a small bottom lateral dimension reduces the contact area of the subsequently formed contact structure, which disadvantageously leads to an increase in electrical resistance and a decrease in the speed and reliability of the semiconductor device.
In addition, using an etch stop layer disadvantageously increases the number of steps in a manufacturing process. As such, the complexity of the overall manufacturing process may be increased, making fabrication of a semiconductor device more difficult to accomplish. In particular, process yield may also be decreased because the addition of one or more process steps may result in a higher probability of forming defects in the semiconductor device. Furthermore, the semiconductor device fabrication may require a longer time period due to the additional process steps. In this manner, overall cost of fabricating a semiconductor device may increase, and manufacturing capacity may be decreased. Moreover, deposition of an etch stop layer may require additional high-temperature processes, which may undesirably alter the properties of structures formed within semiconductor devices. As such, increasing the number of temperatures cycles may produce less robust devices, increased contact resistance, and may prevent the formation of smaller device features.
Therefore, it would be advantageous to develop a system and method for forming openings having substantially perpendicular sidewalls, a high aspect ratio, and acceptable critical dimensions. In particular, it may be advantageous to develop a system and method for etching openings without the use of an etch stop layer to protect underlying layers.